![]() If we had left it at 100 MHz, the simulation would have taken days. Fifty hours is a really long simulation, and therefore we had to lower the clock frequency in the testbench to 10 Hz. To run a 50 hour simulation we gave the command run 50 hr in the ModelSim console. ![]() The waveform zoomed in on the Hours signal: The waveform zoomed in on the Minutes signal: The waveform zoomed in on the Seconds signal: In this video tutorial, we will learn how to create a timer module in VHDL: But it will also react slower because the chain of events becomes longer. We are limited by the available physical resources in the underlying technology as well as the length of the counter versus the clock frequency.Īs the length of the counters increases, obviously, it consumes more resources. We can continue this approach for counting days, weeks, and months too. Similarly, we can create an Hours counter for counting hours, incrementing when 60 minutes have passed. To count minutes, we can implement another Minutes counter which increments when 60 seconds have passed. When this counter reaches the value of the clock frequency, 100 million for example, we know that a second has passed and it’s time to increment another counter. To count seconds in VHDL, we can implement a counter that counts the number of clock periods which passes. This blog post is part of the Basic VHDL Tutorials series. Therefore, if we know that the clock frequency is 100 MHz, we can measure one second by counting a hundred million clock cycles. Every digital design has access to a clock signal which oscillates at a fixed, known frequency. The answer is simply counting clock cycles. So how can we keep track of time in a design module? That only works in simulation because we can’t just tell the electrons in a circuit to pause for a given time. But what about production modules? The wait for statement cannot be used for that. In earlier tutorials we have used the wait for statement to delay time in simulation.
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